1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to a PMOS device with source/drain regions that include in-situ doped epitaxial grown semiconductor materials, such as silicon germanium, and methods of making such a device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors (NMOS) and/or P-channel transistors (PMOS), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon a variety of factors, such as the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length.
There is a constant and continuous drive to increase the performance of NMOS and PMOS transistor devices. One technique for improve such performance is to reduce the channel length of the transistor device. For example, the gate length of such transistors has been dramatically reduced in the past 20 years to improve the switching speed and drive current capability of such devices. The progress has been such that current day transistor devices have gate lengths of approximately 0.3-0.8 μm and further reductions are anticipated in the future. In fact, reducing the physical size of the transistor has progressed so far, and been so effective, that further reductions in the size of such transistors or “scaling” may be difficult to achieve with existing manufacturing tools and techniques. Thus, device designer have resorted to other techniques to improve the performance of NMOS and PMOS transistor devices. In addition to scaling, another technique used to increase the performance of transistor devices has been to incorporate more sophisticated materials into such devices, e.g., the use of metal gate electrodes, the use of so-called high-k dielectric materials (k value greater than 10) and the use of copper based metallization layers. For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. Another technique used to improve device performance is related to establishing certain stresses in the channel region of the transistors. One technique for accomplishing this typically involves forming one or more layers of material, such as silicon nitride, above the transistor that imparts or induces the desired stress in the channel region of the device. In general, it is desirable to create a tensile stress in the channel region of NMOS transistors to increase their performance. In contrast, it is desirable to create a compressive stress in the channel region of the PMOS transistors. The techniques employed in forming such stress inducing layers for selective channel stress engineering purposes are well known to those skilled in the art. Another technique that may be employed to induce the desired compress stress in the channel region of a PMOS device involves forming cavities in the substrate adjacent the gate electrode structure and thereafter epitaxially depositing one or more layer of material, such as silicon germanium, in the cavities. These epitaxially deposited layers tend to induce the desired compressive stress in the channel region of the PMOS device.
One illustrative prior art technique for forming illustrative NMOS and PMOS devices will be described with reference to FIGS. 1A-1F. FIG. 1A is a simplified view of an illustrative semiconductor device 100 at an early stage of manufacturing that is formed above a semiconducting substrate 10. The device 100 generally includes an illustrative PMOS transistor 100P and an illustrative NMOS transistor 100N formed in an PMOS region 10P and an NMOS region 10N, respectively, of the substrate 10. The illustrative transistors 100N, 100P are separated by an illustrative isolation structure 12, e.g., a shallow trench isolation structure, formed in the substrate 10. In one illustrative embodiment, the semiconducting substrate 10 is comprised of bulk silicon. The substrate 10 may have a variety of configurations, like a silicon-on-insulator (SOI) structure having a bulk silicon layer, a buried insulation layer and an active layer.
At the point of fabrication depicted in FIG. 1A, each of the PMOS transistor 100P and the NMOS transistor 100N includes a gate electrode structure 14 that includes an illustrative gate insulation layer 14A and an illustrative gate electrode 14B. Also depicted in FIG. 1A is an illustrative gate cap layer 15, such as silicon nitride. The materials of construction for the gate electrode structures 14 may be different for the PMOS transistor 100P and the NMOS transistor 100N. For example, the NMOS transistor 100N may have a gate insulation layer 14A comprised of silicon dioxide and a gate electrode 14B made of polysilicon, while the PMOS transistor 100P may have a gate insulation layer 14A comprised of a high-k (k greater than 10) dielectric material and a gate electrode 14B made of one or more layers of metal. The configuration and composition of these structures may also vary depending upon the application, and they may be manufactured using techniques well known to those skilled in the art, e.g., deposition of the appropriate layers of material followed by performing one or more etching processes to define the gate electrode structures 14 with the gate cap layer 15 positioned thereabove.
FIG. 1B depicts the device 100 after several operations have been performed. First a layer of spacer material 16, e.g., silicon nitride is blanket-deposited across the device 100. The NMOS region 10N is the covered using a mask layer (not shown). An anisotropic etching process is then performed to for the sidewall spacers 18 adjacent the gate electrode structure 14 of the PMOS device 100P. Next, one or more etching processes are performed to define a plurality of cavities 17 in the substrate 10 in the PMOS region 10P. The size and depth of the cavities 17 may vary depending on the particular application. The spacers 18 act to limit how close the cavities are positioned to the gate electrode structure 14 of the PMOS device 100P. Thereafter, a two-step epitaxial deposition process is performed to form layers 20 and 22 in the cavities 17. In one example, the layer 20 is an undoped, strain inducing, layer of silicon germanium with a germanium content of about 20%. Depending upon the particular application, the thickness of layer 20 may range from 40-50 nm. In one embodiment, the layer 22 is an undoped, layer of silicon. Depending upon the particular application, the thickness of layer 22 may range from 15-20 nm.
Next, as shown in FIG. 1C, in one example, one or more etching process are performed to remove the layer of spacer material 16 and the spacers 18. Then, as shown in FIG. 1D, sidewall spacers 24 are formed adjacent the gate electrode structures 14 of the PMOS transistor 100P and the NMOS transistor 100N using known techniques. At this point, various ion implantation processes are performed to form certain doped region, e.g., halo implant regions, extension implant regions, etc., in the substrate 10. For clarity, the halo implant regions and the extension implant regions are not depicted in the drawings. These implant regions are made using known implant techniques and dopant materials.
Next, as shown in FIG. 1E, additional spacers 26 are formed adjacent the spacers 24 using known techniques and materials. The spacers 26 are added to properly locate the deep source/drain implant regions that will be formed next by performing known ion implant techniques using dopant materials that are known to those skilled in the art. Again, for clarity, the deep source/drain implant regions are not depicted in FIG. 1E.
Next, the device 100 may be subjected to one or more heating process to repair damage to the lattice structure of the substrate 10 resulting from the ion implantation processes, and to activate the implanted dopant materials. In one example, a rapid thermal anneal process is performed followed by performing a very quick, millisecond ultra-fast anneal (UFA) process. This results in the schematically depicted source/drain regions 30 depicted in FIG. 1F. Thereafter, the device is subjected to additional processing operations to complete fabrication of the device 100; e.g., the formation of metal silicide regions on the source/drain regions 30, the formation of various contacts and metallization layers, etc.
One problem associated with the prior art process flow described above is that the layers 20, 22 are subjected to the implantation processes described above: halo implant, extension implant and source/drain implants, and suffer the associated damage to the lattice structure of those layers 20, 22. Additionally, when the layers 20, 22 are subjected to the heating processes to repair the damaged lattice structure and to activate the implanted ions, the layers 20, 22 tend to relax and, as a result, impart less compressive stress to the channel region of the PMOS device 100P. In turn, this reduction in compressive stress tends to reduce the performance capabilities of the PMOS device 100P and the resulting semiconductor device 100 that includes such a PMOS device 100P.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.